The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device adopting an interlayer contact structure for improving the electrical characteristics of the device by reducing the contact resistance between upper and lower conductive layers thereof, and a method of manufacturing the same.
As the integration of semiconductor devices increases, the formation of conductive layers having a multi-layered structure becomes more prevalent. In doing so, the contact characteristic (i.e., resistance) between such conductive layers has an important effect on the overall electrical characteristics of the semiconductor device. Recently, a conductive layer having a polycide structure (silicide atop polysilicon) has been employed to reduce sheet resistance.
FIGS. 1A-1D illustrate a conventional method for making an interlayer contact between upper and lower conductive layers, each having the above-mentioned polycide structure, of a semiconductor memory device.
Referring to FIG. 1A, an oxide such as silicon oxide (SiO.sub.2) is deposited on a semiconductor substrate 10 to form a gate oxide layer 12. Then, a first polysilicon layer 14 doped with phosphorus ions, a first tungsten silicide (WSi.sub.x) layer 16 and a capping layer 18 are sequentially deposited on the gate oxide layer 12, and are then patterned to form a lower conductive layer out of the first polysilicon layer 14 and the first tungsten silicide layer 16. The capping layer 18 is generally formed out of an oxide or nitride material. Then, an insulating material such as boro-phosphorus silicate glass is deposited over the first tungsten silicon layer 16, and is reflowed to form an interlayer insulating layer 20 having a planer surface (see FIG. 1B). A contact hole I is then formed by partially etching the interlayer insulating layer 20 and the capping layer 18 to expose the first tungsten silicide layer 16 (see FIG. 1C). Subsequently, a second polysilicon layer 22 doped with phosphorus ions and a second tungsten silicide layer 24 are stacked over the interlayer insulating layer 20 and the second tungsten silicon layer to form an upper conductive layer. The contact layer is formed such that the second polysilicon layer 22 is in contact with first tungsten silicide layer 16 (see FIG. 1D).
In this conventional interlayer contact structure, however, where the first tungsten silicide layer 16 directly contacts the second polysilicon layer 22, and the second polysilicon layer 22 is doped with phosphorus ions, the contact resistance increases for two reasons. First, the phosphorus ions doped in the second polysilicon layer 22 diffuse toward the first tungsten silicide layer 16, and serve to decrease the impurity concentration at the interface between the second polysilicon layer 22 and the first tungsten silicon layer. Secondly, after forming the contact hole 1 and prior to depositing the second polysilicon layer 22, a natural oxide layer such as tungsten oxide (WO.sub.3) or silicon oxide (SiO.sub.2) forms on the surface of first tungsten silicide layer 16.
FIG. 2 shows the contact resistance distribution characteristics measured in seven sample wafers (a) through (g) that adopt the conventional interlayer contact structure (FIG. 1D). Here, it can be seen that the contact resistance of the conventional contact structure runs well above 1 k.OMEGA. per contact (where the contact size is about 0.4-0.48 mm.sup.2). Such a high contact resistance negatively affects the operation speed and can even prevent proper device operation if it goes beyond about 10 kW.
FIG. 3 shows the impurities distribution in the contact structure described above, both before (a) and after (b) annealing. Concentrations are shown for the first polysilicon layer 14, the first tungsten silicide layer 16, the second polysilicon layer 22, the second tungsten silicide layer 24, and at every interface of these layers. Here, a low concentration of impurities is evident between the first tungsten silicide layer 16 and the second polysilicon layer 22.